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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
108-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
劉宗德 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
02 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四8(15:30~16:20)星期五8,9(15:30~17:20) |
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上課地點 |
電二229電二229 |
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備註 |
本系優先
總人數上限：60人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1081EE2012_02 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Tentative Class Topics
1. Introduction: Number Systems and Conversion
2. Boolean Algebra
3. Boolean Algebra (continued)
4. Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. K-Maps
7. Multi-Level Gate Circuits: NAND and NOR Gates
8. Combinational Circuit Design and Simulation Using Gates
9. Multiplexers, Decodes and PLD
10. Latches and FFs
11. Registers and Counters
12. Analysis of Clocked Sequential Circuits
13. Derivation of State Graphs and Tables
14. Reduction of State Tables and State Assignment
15. Sequential Circuit Design
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課程目標 |
Students will learn how to use logic gates and sequencing elements to design digital circuits. |
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課程要求 |
待補 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning. |
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參考書目 |
待補 |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Quiz1 |
5% |
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2. |
Quiz2 |
5% |
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3. |
Quiz3 |
5% |
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4. |
Quiz4 |
5% |
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5. |
Midterm |
35% |
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6. |
Quartus II HW |
10% |
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7. |
Final |
35% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/12, 9/13 |
09/12：Ch 1 Intro, Number Systems
09/13：Moon Festival (中秋節) |
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第2週 |
9/19, 9/20 |
09/19：Ch 1 (cont'd) / Ch 2 Boolean Algebra
09/20：Ch 2 (cont'd) |
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第3週 |
9/26, 9/27 |
09/26：Ch 3 Boolean Algebra (Continued)
09/27：Ch 3 (cont’d) |
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第4週 |
10/03, 10/04 |
10/03：Quiz 1 (Ch1-3)
10/04：Ch 4 Applications of Boolean Algebra |
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第5週 |
10/10, 10/11 |
10/10：The National Day
10/11：The National Day |
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第6週 |
10/17, 10/18 |
10/17：Ch 5 Karnaugh Maps
10/18：Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
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第7週 |
10/24, 10/25 |
10/24：Quiz 2 (Ch4, 5)
10/25：Ch 8 Combinational Ckt Design (skip Fig 8-12, 8-14) |
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第8週 |
10/31, 11/01 |
10/31：Ch 9 Multiplexers Decoders and PLDs (skip 9.7, 9.8, and Shannon’s expansion (eqs. 9-10~12) will be included in the exam.)
11/01：Ch 9 (cont'd) |
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第9週 |
11/07, 11/08 |
11/07：Review Session
11/08：Midterm (Ch1-5, 7-9) |
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第10週 |
11/14, 11/15 |
11/14：Ch 11 Latches and FFs
11/15：University Anniversary |
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第11週 |
11/21, 11/22 |
11/21：Ch 11 Latches and FFs / Ch 12 Registers and Counters
11/22：Combinational Circuit Design using Altera Quartus II
- Quartus II HW1 (due 12/13) |
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第12週 |
11/28, 11/29 |
11/28：Ch 12 (cont’d)
11/29：Ch 12 (cont’d) / Ch 13 Analysis of Clocked Sequential Ckts |
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第13週 |
12/05, 12/06 |
12/05：Quiz 3 (Ch11-12)
12/06：Sequential Circuit Design using Altera Quartus II
- Quartus II HW2 (due 01/10) |
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第14週 |
12/12, 12/13 |
12/12：Ch 13 (cont’d)
12/13：Ch 14 Derivation of State Graphs and Tables (Skip Examples 2 & 3 in Sec. 14.3) |
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第15週 |
12/19, 12/20 |
12/19：Ch 14 (cont’d)
12/20：Ch 15 Reduction of State Tables (15.1 to 15.3) |
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第16週 |
12/26, 12/27 |
12/26：Quiz 4 (Ch13-14)
12/27：Ch 15 (cont’d) / Ch 16 Sequential Ckt Design (16.1 to 16.4) |
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第17週 |
01/02, 01/03 |
01/02：Ch 16 (cont’d)
01/03：Supplementary Materials |
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第18週 |
01/09, 01/10 |
01/09：Review Session
01/10：Final Exam (Ch 11-16) |
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